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UJA1065
High-speed CAN/LIN fail-safe system basis chip
Rev. 01 -- 10 August 2005 Objective data sheet
1. General description
The UJA1065 System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and a Local Interconnect Network (LIN) interface. The SBC supports all networking applications which control various power and sensor peripherals by using high-speed CAN as the main network interface and LIN as a local sub-bus. The SBC contains the following integrated devices:
* High-speed CAN transceiver, inter-operable and downwards compatible with CAN
transceiver TJA1041 and TJA1041A, and compatible with the ISO11898-2 standard and the ISO11898-5 standard (in preparation)
* * * * * *
LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3 Advanced independant watchdog Dedicated voltage regulators for microcontroller and CAN transceiver Serial peripheral interface (full duplex) Local wake-up input port Inhibit / limp home output port
In addition to the advantages of integrating these common ECU functions in a single package, the SBC offers an intelligent combination of system-specific functions such as:
* * * *
Advanced low power concept Safe and controlled system start-up behavior Advanced fail-safe system behavior that prevents any conceivable deadlock Detailed status reporting on system and sub-system levels
The UJA1065 is designed to be used in combination with a microcontroller with a CAN controller. The SBC ensures that the microcontroller is always started up in a defined manner. In failure situations the SBC will maintain the microcontroller function for as long as possible, to provide full monitoring and software driven fall-back operation. The UJA1065 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures.
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
2. Features
2.1 General
s Contains a full set of CAN and LIN ECU functions: x CAN transceiver and LIN transceiver x Voltage regulator for the microcontroller (3.0 V, 3.3 V or 5.0 V) x Separate voltage regulator for the CAN transceiver (5 V) x Enhanced window watchdog with on-chip oscillator x Serial Peripheral Interface (SPI) for the microcontroller x ECU power management system x Fully integrated autonomous fail-safe system s Designed for automotive applications: x Supports 14 V, 24 V and 42 V architectures x Excellent ElectroMagnetic Compatibility (EMC) performance x 8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off board pins x 60 V short-circuit proof CAN / LIN-bus pins x Battery and CAN / LIN-bus pins are protected against transients in accordance with ISO 7637 x Very low Sleep current s Supports remote flash programming via the CAN-bus s Small 8 mm x 11 mm HTSSOP32 package with low thermal resistance
2.2 CAN transceiver
s ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver s Enhanced error signalling and reporting s Dedicated low dropout voltage regulator for the CAN-bus: x Independent from microcontroller supply x Guarded by CAN-bus failure management x Significantly improves EMC performance s Partial networking option with global wake-up feature, allows selective CAN-bus communication without waking up sleeping nodes s Bus connections are truly floating when power is off s SPLIT output pin for stabilizing the recessive bus level
2.3 LIN transceiver
s LIN 2.0 compliant LIN transceiver s Enhanced error signalling and reporting s Downward compatible with LIN 1.3 and the TJA1020
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Objective data sheet
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
2.4 Power management
s s s s s Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep mode Local wake-up input with cyclic supply feature Remote wake-up capability via the CAN-bus and LIN-bus External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe) s 42 V battery related high-side switch for driving external loads such as relays and wake-up switches s Intelligent maskable interrupt output
2.5 Fail-safe features
s Safe and predictable behavior under all conditions s Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision s Fail-safe coded 16-bit SPI interface for the microcontroller s Global enable pin for the control of safety critical hardware s Detection and detailed reporting of failures: x On-chip oscillator failure and watchdog alerts x Battery and voltage regulator undervoltages x CAN and LIN-bus failures (short-circuits and open-circuit bus wires) x TXD and RXD clamping situations and short-circuits x Clamped or open reset line x SPI message errors x Overtemperature warning x ECU ground shift (two selectable thresholds) s Rigorous error handling based on diagnostics s Supply failure early warning allows critical data to be stored s 23 bits of access-protected RAM is available e.g. for logging of cyclic problems s Reporting in a single SPI message; no assembly of multiple SPI frames needed s Limp home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights) s Fail-safe coded activation of Software development mode and Flash mode s Unique SPI readable device type identification s Software initiated system reset
3. Ordering information
Table 1: Ordering information Package Name UJA1065TW HTSSOP32 Description Version plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1 body width 6.1 mm; lead pitch 0.65 mm; exposed die pad Type number
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
4. Block diagram
SENSE BAT42 BAT14
31 32 27 BAT MONITOR V1
UJA1065
4 V1
SYSINH V3 INH/LIMP
29 30 17
V2
20
V2
INH V1 MONITOR
INTN WAKE TEST
7 18 16 CHIP TEMPERATURE SBC FAIL-SAFE SYSTEM WAKE RESET/EN 6 8 RSTN EN
WATCHDOG
SCK SDI SDO SCS
11 9 10 12 SPI GND SHIFT DETECTOR OSCILLATOR
RTLIN LIN TXDL RXDL GND
26 25 3 5 23 LIN HIGH SPEED CAN BAT42 BAT42 V2 21 22 13 14 24
SPLIT CANH CANL TXDC RXDC
001aac305
Fig 1. Block diagram
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
5. Pinning information
5.1 Pinning
n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI
1 2 3 4 5 6 7 8 9
32 BAT42 31 SENSE 30 V3 29 SYSINH 28 n.c. 27 BAT14 26 RTLIN 25 LIN 24 SPLIT 23 GND 22 CANL 21 CANH 20 V2 19 n.c. 18 WAKE 17 INH/LIMP
001aac306
UJA1065TW
SDO 10 SCK 11 SCS 12 TXDC 13 RXDC 14 n.c. 15 TEST 16
Fig 2. Pin configuration
5.2 Pin description
Table 2: Symbol n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCS TXDC RXDC n.c. TEST
9397 750 14409
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description not connected not connected LIN transmit data input (LOW for dominant, HIGH for recessive) voltage regulator output for the microcontroller (3 V, 3.3 V or 5 V depending on the SBC version) LIN receive data output (LOW when dominant, HIGH when recessive) reset output to microcontroller (active LOW; will detect clamping situations) interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to other ECU interrupt outputs) enable output (active HIGH; push-pull, LOW with every reset / watchdog overflow) SPI data input SPI data output (floating when pin SCS is HIGH) SPI clock input SPI chip select input (active LOW) CAN transmit data input (LOW for dominant; HIGH for recessive) CAN receive data output (LOW when dominant; HIGH when recessive) not connected test pin (should be connected to ground in application)
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
Pin description ...continued Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description inhibit / limp home output (BAT14 related, push-pull, default floating) local wake-up input (BAT42 related, continuous or cyclic sampling) not connected 5 V voltage regulator output for CAN; connect a buffer capacitor to this pin CANH bus line (HIGH in dominant state) CANL bus line (LOW in dominant state) ground CAN-bus common mode stabilization output LIN bus line (LOW in dominant state) LIN-bus termination resistor connection 14 V battery supply input not connected system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC converter) unregulated 42 V output (BAT42 related; continuous output, or cyclic mode synchronized with local wake-up input) fast battery interrupt / chatter detector input 42 V battery supply input (connect this pin to BAT14 in 14 V applications)
Table 2: Symbol INH/LIMP WAKE n.c. V2 CANH CANL GND SPLIT LIN RTLIN BAT14 n.c. SYSINH V3 SENSE BAT42
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
6. Functional description
6.1 Introduction
The UJA1065 combines all peripheral functions around a microcontroller within typical automotive networking applications into one dedicated chip. The functions are as follows:
* * * * * * * * * * * * *
Power supply for the microcontroller Power supply for the CAN transceiver Switched BAT42 output System reset Watchdog with Window mode and Time-out mode On-chip oscillator High-speed CAN and LIN transceivers for serial communication; suitable for 12 V, 24 V and 42 V applications SPI control interface Local wake-up input Inhibit or limp home output System inhibit output port Compatibility with 42 V power supply systems Fail-safe behavior
6.2 Fail-safe system controller
The fail-safe system controller is the core of the UJA1065 and is supervised by a watchdog timer which is clocked directly by the dedicated on-chip oscillator. The system controller manages the register configuration and controls all internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The fail-safe system controller is a state machine. The different operating modes and the transitions between these modes are illustrated in Figure 3. The following sections give further details about the SBC operating modes.
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
mode change via SPI
watchdog trigger
Standby mode
V1: ON SYSINH: HIGH CAN: on-line/on-line listen/off-line LIN: off-line watchdog: time-out/OFF INH/LIMP: HIGH/LOW/float EN: HIGH/LOW
mode change via SPI
mode change via SPI
watchdog trigger
Normal mode
V1: ON SYSINH: HIGH CAN: all modes available LIN: all modes available watchdog: window INH/LIMP: HIGH/LOW/float EN: HIGH/LOW
wake-up detected with its wake-up interrupt disabled OR mode change to Sleep with pending wake-up OR watchdog time-out with watchdog timeout interrupt disabled OR watchdog OFF and IV1 > I thH(V1) with reset option OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected flash entry enabled (111/001/111 mode sequence) OR illegal Mode register code OR mode change to Sleep with pending wake-up OR watchdog not properly served OR interrupt ignored > tRSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code mode change via SPI
Sleep mode
V1: OFF SYSINH: HIGH/float CAN: on-line/on-line listen/off-line LIN: off-line watchdog: time-out/OFF INH/LIMP: LOW/float RSTN: LOW EN: LOW
init Normal mode via SPI successful
wake-up detected OR watchdog time-out OR V3 overload detected
Start-up mode
V1: ON SYSINH: HIGH CAN: on-line/on-line listen/off-line LIN: off-line watchdog: start-up INH/LIMP: HIGH/LOW/float EN: LOW
init Normal mode via SPI successful
supply connected for the first time
init Flash mode via SPI AND flash entry enabled
t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code
Restart mode
V1: ON SYSINH: HIGH CAN: on-line/on-line listen/off-line LIN: off-line watchdog: start-up INH/LIMP: LOW/float EN: LOW t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code wake-up detected AND oscillator ok AND t > t ret
leave Flash mode code OR watchdog time-out OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code
watchdog trigger
Flash mode
V1: ON SYSINH: HIGH CAN: all modes available LIN: all modes available watchdog: time-out/OFF INH/LIMP: HIGH/LOW/float EN: HIGH/LOW
Fail-safe mode
V1: OFF SYSINH: HIGH/float CAN: on-line/on-line listen/off-line LIN: off-line watchdog: OFF INH/LIMP: LOW RSTN: LOW EN: LOW oscillator fail OR RSTN externally clamped HIGH detected > t RSTN(CHT) OR RSTN externally clamped LOW detected > t RSTN(CLT) OR RSTN released and V1 undervoltage detected > t V1(CLT)
from any mode
001aad180
Fig 3. Main state diagram
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High-speed CAN/LIN fail-safe system basis chip
6.2.1 Start-up mode
Start-up mode is the `home page' of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a system reset. The reset source information is provided by the SBC to support different software initialization cycles that depend on the reset event. It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode or Fail-safe mode. Such a wake-up can originate either from the CAN-bus, the LIN-bus or from the local WAKE pin. On entering Start-up mode a lengthened reset time tRSTNL is observed. This reset time is either user defined (via the RLC bit in the System Configuration register) or defaults to the value as given in Section 6.13.12. During the reset lengthening time pin RSTN is held LOW by the SBC. When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog timer will wait for initialization. If the watchdog initialization is successful, the selected operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart mode will be entered.
6.2.2 Restart mode
The purpose of the Restart mode is to give the application a second chance to start up, should the first attempt from Start-up mode fail. Entering Restart mode will always set the reset lengthening time tRSTNL to the higher value to guarantee the maximum reset length, regardless of previous events. If start-up from Restart mode is successful (the previous problems do not reoccur and watchdog initialization is successful), then the selected operating mode will be entered. From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up, then Fail-safe mode will be entered.
6.2.3 Fail-safe mode
Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible system power consumption from the SBC and from the external components controlled by the SBC. A wake-up (via the CAN-bus, the LIN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe mode with a defined delay tret, to guarantee a discharged V1 before entering Start-up mode. Regulator V1 will restart and the reset lengthening time tRSTNL is set to the higher value; see Section 6.5.1.
6.2.4 Normal mode
Normal mode gives access to all SBC system resources, including CAN, LIN, INH/LIMP and EN. Therefore in Normal mode the SBC watchdog runs in (programmable) window mode, for strictest software supervision. Whenever the watchdog is not properly served a system reset is performed. Interrupts from SBC to the host microcontroller are also monitored. A system reset is performed if the host microcontroller does not respond within tRSTN(INT).
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Entering Normal mode does not activate the CAN transceiver automatically. The CAN Mode Control (CMC) bit must be used to activate the CAN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus.
6.2.5 Standby mode
In Standby mode the system is set into a state with reduced current consumption. Entering Standby mode automatically clears the CMC bit, allowing the CAN transceiver to enter the low-power mode autonomously. The watchdog will, however, continue to monitor the microcontroller (time-out mode) since it is powered via pin V1. In the event that the host microcontroller can provide a low-power mode with reduced current consumption in its standby or stop mode, the watchdog can be switched off entirely in Standby mode of the SBC. The SBC monitors the microcontroller supply current to ensure that there is no unobserved phase with disabled watchdog and running microcontroller. The watchdog will remain active until the supply current drops below IthL(V1). Below this current limit the watchdog is disabled. Should the current increase to IthH(V1), e.g. as result of a microcontroller wake-up from application specific hardware, the watchdog will start operating again with the previously used time-out period. If needed, an interrupt can be issued when the watchdog restarts. If the watchdog is not triggered correctly, a system reset will occur and the SBC will enter Start-up mode. If Standby mode is entered from Normal mode with the selected watchdog OFF option, the watchdog will use the maximum time-out as defined for Standby mode until the supply current drops below the current detection threshold; the watchdog is now OFF. If the current increases again, the watchdog is immediately activated, again using the maximum watchdog time-out period. If the watchdog OFF option is selected during Standby mode, the last used watchdog period will define the time for the supply current to fall below the current detection threshold. This allows the user to align the current supervisor function to the application needs. Generally, the microcontroller can be activated from Standby mode via a system reset or via an interrupt without reset. This allows implementation of differentiated start-up behavior from Standby mode, depending on the application needs:
* If the watchdog is still running during Standby mode, the watchdog can be used for
cyclic wake-up behavior of the system. A dedicated Watchdog Time-out Interrupt Enable (WTIE) bit enables the microcontroller to decide whether to receive an interrupt or a hardware reset upon overflow. The interrupt option will be cleared in hardware automatically with each watchdog overflow to ensure that a failing main routine is detected while the interrupt service still operates. So the application software must set the interrupt behavior each time before a standby cycle is entered.
* Any wake-up via the CAN-bus or the LIN-bus together with a local wake-up event will
force a system reset event or an interrupt to the microcontroller. So it is possible to exit Standby mode without any system reset if required. When an interrupt event occurs the application software has to read the Interrupt register within tRSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be entered. If the application has read out the Interrupt register within the specified time, it can decide whether to switch into Normal mode via an SPI access or to stay in Standby mode.
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The following operations are possible from Standby mode:
* Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
* Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start sequences after reset)
* Wake-up by activity on the CAN-bus or LIN-bus via an interrupt signal to the
microcontroller
* Wake-up by bus activity on the CAN-bus or LIN-bus via a reset signal * Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid and wake-up from an external application not connected to the SBC)
* Wake-up by increasing the microcontroller supply current with a reset signal * Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller * Wake-up due to a falling edge at pin WAKE forcing a reset signal
6.2.6 Sleep mode
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled external supplies are switched off entirely, resulting in minimum system power consumption. In this mode, the watchdog runs in time-out mode or is completely off. Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is disabled. Only pin SYSINH can remain active to support the V2 voltage supply; this depends on the CAN programming. It is also possible for V3 to be on, off or in cyclic mode to supply external wake-up switches. If the watchdog is not disabled in software, it will continue to run and force a system reset upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1 becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode. Depending on the application, the following operations can be selected from Sleep mode:
* Cyclic wake-up by the watchdog (only in time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow different start sequences after reset
* Wake-up by activity on the CAN-bus, LIN-bus or falling edge at pin WAKE * An overload on V3, only if V3 is in a cyclic or in continuously on mode
6.2.7 Flash mode
Flash mode can only be entered from Start-up mode by entering a specific Flash mode entry sequence. This fail-safe control sequence comprises three consecutive write accesses to the Mode register, within the legal windows of the watchdog, using the operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the SBC will enter Start-up mode and perform a system reset with the related reset source information (RSS = 0110).
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High-speed CAN/LIN fail-safe system basis chip
From Start-up mode the application software now has to enter Flash mode within tWD(init) by writing Operating Mode code 011 to the Mode register. This feeds back a successfully received hardware reset (handshake between the SBC and the microcontroller). The transition from Start-up mode to Flash mode is possible only once after completing the Flash entry sequence. The application can also decide not to enter Flash mode but to return to Normal mode by using the Operating Mode code 101 for handshaking. This erases the Flash mode entry sequence. The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode, but Operating Mode code 111 must be used for serving the watchdog. If this code is not used or if the watchdog overflows, the SBC immediately forces a reset and enters Start-up mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash mode), which results in a system reset with the corresponding reset source information. Other Mode register codes will cause a forced reset with reset source code `illegal Mode register code'.
6.3 On-chip oscillator
The on-chip oscillator provides the clock signal for all digital functions and is the timing reference for the on-chip watchdog and the internal timers. If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the oscillator has recovered to its normal frequency and the system receives a wake-up event.
6.4 Watchdog
The watchdog provides the following timing functions:
* Start-up mode; needed to give the software the opportunity to initialize the system * Window mode; detects too early and too late accesses in Normal mode * Time-out mode; detects a too late access, can also be used to restart or interrupt the
microcontroller from time to time (cyclic wake-up function)
* OFF mode; fail-safe shut-down during operation thus preventing any blind spots in the
system supervision The watchdog is clocked directly by the on-chip oscillator. To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are coded with redundant bits. Therefore, only certain codes are allowed for a proper watchdog service. The following corrupted watchdog accesses result in an immediate system reset:
* Illegal watchdog period coding; only ten different codes are valid * Illegal operating mode coding; only six different codes are valid
Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register. This enables an easy software flow control with defined watchdog behavior when switching between different software modules.
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6.4.1 Watchdog start-up behavior
Following any reset event the watchdog is used to monitor the ECU start-up procedure. It observes the behavior of the RSTN pin for any clamping condition or interrupted reset wire. In case the watchdog is not properly served within tWD(init), another reset is forced and the monitoring procedure is restarted. In case the watchdog is again not properly served, the system enters Fail-safe mode (see also Figure 3, Startup and Restart mode).
6.4.2 Watchdog window behavior
Whenever the SBC enters Normal mode, the window mode of the watchdog is activated. This ensures that the microcontroller operates within the required speed; a too fast as well as a too slow operation will be detected. Watchdog triggering using the Window mode is illustrated in Figure 4.
period
too early trigger restarts period trigger via SPI last trigger point 50 %
trigger window 100 %
earliest possible trigger point trigger restarts period (with different duration if desired)
latest possible trigger point
50 % too early trigger window
100 %
new period
trigger via SPI earliest possible trigger point latest possible trigger point
mce626
Fig 4. Watchdog triggering using Window mode
The SBC provides 10 different period timings, scalable with a 4 factor watchdog prescaler. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time, the timer will be reset to start a new period. The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period. Any too early or too late watchdog access or wrong Mode register code access will result in an immediate system reset, entering Start-up mode.
6.4.3 Watchdog time-out behavior
Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active watchdog operates in Time-out mode. The watchdog has to be triggered within the actual programmed period time; see Figure 5. The Time-out mode can be used to provide cyclic wake-up events to the host microcontroller from Standby and Sleep mode.
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period
trigger range
time-out
trigger via SPI earliest possible trigger point trigger restarts period (with different duration if desired) latest possible trigger point
trigger range new period
time-out
mce627
Fig 5. Watchdog triggering using Time-out mode
In Standby and in Flash mode the nominal periods can be changed with any SPI access to the Mode register. Any illegal watchdog trigger code results in an immediate system reset, entering Start-up mode.
6.4.4 Watchdog OFF behavior
In Standby and Sleep mode it is possible to switch off the watchdog entirely. For fail-safe reasons this is only possible if the microcontroller has stopped program execution. To ensure that there is no program execution, the V1 supply current is monitored by the SBC while the watchdog is switched off. When selecting the watchdog OFF code, the watchdog remains active until the microcontroller supply current has dropped below the current monitoring threshold IthL(V1). After the supply current has dropped below the threshold, the watchdog stops at the end of the watchdog period. In case the supply current does not drop below the monitoring threshold, the watchdog stays active. If the microcontroller supply current increases above IthH(V1) while the Watchdog is OFF, the watchdog is restarted with the last used watchdog period time and a watchdog restart interrupt is forced, if enabled. In case of a direct mode change towards Standby Mode with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that in Sleep mode V1 current monitoring is not active.
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6.5 System reset
The reset function of the UJA1065 offers two signals to deal with reset events:
* RSTN; the global ECU system reset * EN; a fail-safe global enable signal
6.5.1 RSTN pin
The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with selectable pulse length upon the following events; see Figure 3:
* Power-on (first battery connection) or BAT42 below Power-on reset threshold voltage * Low V1 supply * V1 current above threshold during Standby mode while watchdog OFF behavior is
selected
* * * * * * * * *
V3 is down due to short-circuit condition during Sleep mode RSTN externally forced LOW, falling edge event Successful preparation for Flash mode completed Successful exit from Flash mode Wake-up from Standby mode via pins CAN, LIN or WAKE if programmed accordingly, or any wake-up event from Sleep mode Wake-up event from Fail-safe mode Watchdog trigger failures (too early, overflow, wrong code) Illegal mode code via SPI applied Interrupt not served within tRSTN(INT)
All of these reset events have a dedicated reset source in the System Status register to allow distinction between the different events. The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware is properly reset. After the first battery connection, a short Power-on reset of 1 ms is provided after voltage V1 is present. Once started, the microcontroller can set the Reset Length Control (RLC) bit within the System Configuration Register; this allows the reset pulse to be adjusted for future reset events. With this bit set, all reset events are lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms) in Restart mode or with an externally applied falling edge at pin RSTN. With this mechanism it is guaranteed that an erroneously shortened reset pulse will restart any microcontroller, at least within the second trial by using the long reset pulse. The behavior of pin RSTN is illustrated in Figure 6. The duration of tRSTL depends on the setting of the RLC bit (defines the reset length). Once an external reset event is detected the system controller enters the Start-up mode. The watchdog now starts to monitor pin RSTN as illustrated in Figure 7. If the RSTN pin is not released in time then Fail-safe mode is entered as shown in Figure 3.
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V1
VUH: release level VUL: detection level
VRV1
VRV2 time
power-up VRSTN
undervoltage
missing watchdog access
undervoltage spike
powerdown
time tRSTL tRSTL tRSTL
mce628
Fig 6. Reset pin behavior
VRSTN
time t RSTNL RSTN externally forced LOW t WD(init)
VRSTN
time t RSTNL RSTN externally forced LOW t WD(init)
001aad181
Fig 7. Reset timing diagram
Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer than tRSTN(ext), the SBC immediately enters Fail-safe mode since this indicates an application failure.
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The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin for longer than tRSTN(ext) while pin RSTN is driven internally to a LOW-level by the SBC, the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be reset any more. By entering Fail-safe mode, the V1 voltage regulator shuts down and the microcontroller stops. Additionally, chattering reset signals are handled by the SBC in such a way that the system safely falls back to Fail-safe mode with the lowest possible power consumption.
6.5.2 EN output
Pin EN can be used to control external hardware such as power components or as a general purpose output if the system is running properly. During all reset events, when pin RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the microcontroller can set the EN control bit via the SPI. This results in releasing pin EN which then returns to a HIGH-level.
6.6 Power supplies
6.6.1 BAT14, BAT42 and SYSINH
The SBC has two supply pins, pin BAT42 and pin BAT14. Pin BAT42 supplies most of the SBC where pin BAT14 only supplies the linear voltage regulators and the INH/LIMP output pin. This supply architecture allows different supply strategies including the use of external DC-to-DC converters controlled by the pin SYSINH.
6.6.2 SENSE input
The SBC has a dedicated SENSE pin for dynamic monitoring of the battery contact of an electronic control unit. Connecting this pin in front of the polarity protection diode of the ECU provides an early warning if the battery becomes disconnected.
6.6.3 Voltage regulators V1 and V2
The UJA1065 has two independent voltage regulators supplied out of the BAT14 pin. Regulator V1 is intended to supply the microcontroller. Regulator V2 is reserved for the high-speed CAN transceiver. 6.6.3.1 Voltage regulator V1 The V1 voltage is continuously monitored to provide the system reset signal when undervoltage situations occur. Whenever the V1 voltage falls below one of the three programmable thresholds, a hardware reset is forced. A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events lower than VUV(VF1). This allows the application to receive a supply warning interrupt in case one of the lower V1 undervoltage reset thresholds is selected. The V1 regulator is overload protected. The maximum output current available from pin V1 depends on the voltage applied to pin BAT14 according to the characteristics section. For thermal reasons, the total power dissipation should be taken into account.
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6.6.3.2
Voltage regulator V2 Voltage regulator V2 provides a 5 V supply for the CAN transmitter. The pin V2 is intended for the connection of external buffering capacitors. V2 is controlled autonomously by the CAN transceiver control system and is activated on any detected CAN-bus activity, or if the CAN transceiver is enabled by the application microcontroller. V2 is short-circuit protected and will be disabled in case of an overload situation. Dedicated bits in the System Diagnosis register and the Interrupt register provide V2 status feedback to the application. Besides the autonomous control of V2 there is a software accessible bit which allows activation of V2 manually (V2C). This allows V2 to be used for other application purposes when CAN is not actively used (e.g. while CAN is off-line). Generally, V2 should not be used for other application hardware while CAN is in use. If the regulator V2 is not able to start within the V2 clamped LOW time (> tV2(CLT)), or if a short-circuit has been detected during an already activated V2, then V2 is disabled and the V2D bit in the Diagnosis register is cleared. Additionally the CTC bit in the Physical Layer register is set and the V2C bit is cleared. Reactivation of voltage regulator V2 can be done by:
* * * *
Clearing the CTC bit while CAN is in Active mode Wake up via CAN while CAN is not in Active mode Setting the V2C bit When entering CAN Active mode
6.6.4 Switched battery output V3
V3 is a high-side switched BAT42-related output which is used to drive external loads such as wake-up switches or relays. The features of V3 are as follows:
* Three application controlled modes of operation; On, Off or Cyclic mode. * Two different cyclic modes allow the supply of external wake-up switches; these
switches are powered intermittently, thus reducing the system's power consumption in case a switch is continuously active; the wake-up input of the SBC is synchronized with the V3 cycle time.
* The switch is protected against current overloads. If V3 is overloaded, pin V3 is
automatically disabled. The corresponding Diagnosis register bit is reset and an interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the corresponding reset source code becomes available in the RSS bits of the System Status register. This signals that the wake-up source via V3 supplied wake-up switches has been lost.
6.7 CAN transceiver
The integrated high-speed CAN transceiver of the UJA1065 is an advanced ISO11898-2 / ISO11898-5 compliant transceiver. In addition to standard high-speed CAN transceivers the UJA1065 transceiver provides the following features:
* Enhanced error handling and reporting of bus and RXD/TXD failures; these failures
are separately identified in the System Diagnosis register
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* Integrated autonomous control system for determining the mode of the CAN
transceiver
* Ground shift detection with two selectable warning levels, to detect possible local
ground problems before the CAN communication is affected
* On-line Listen mode with global wake-up message filter allows partial networking * Bus connections are truly floating when power is off
6.7.1 Mode control
The controller of the CAN transceiver provides four modes of operation: Active mode, On-line mode, On-line Listen mode and Off-line mode; see Figure 8. In the Diagnosis register two dedicated CAN status bits (CANMD) are available to signal the mode of the transceiver.
Active mode
V2 : ON/OFF (V2D) transmitter: ON/OFF (CTC) RXDC: bit stream/HIGH (V2D) SPLIT: ON/OFF (CSC/V2D) CPNC = 0
CMC = 1
CMC = 0 AND CPNC = 1
CMC = 0 AND CPNC = 0
CMC = 1
On-line mode
V2 : ON/OFF (V2C/V2D) transmitter: OFF RXDC: wake-up (active LOW) SPLIT: ON/OFF (CSC/V2D) CPNC = 0
CPNC = 1
On-line Listen mode
V2 : ON/OFF (V2C/V2D) transmitter: OFF RXDC: V1 SPLIT: ON/OFF (CSC/V2D) CMC = 1
global wake-up message detected OR CPNC = 0
no activity for t > t off-line
CAN wake-up filter passed AND CPNC = 1
CAN wake-up filter passed AND CPNC = 0
no activity for t > t off-line
Off-line mode
power-on V2 : ON/OFF (V2C/V2D) transmitter: OFF RXDC: V1 SPLIT: OFF
001aad182
Fig 8. States of the CAN transceiver
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6.7.1.1
Active mode In Active mode the CAN transceiver can transmit data to and receive data from the CAN bus. To enter Active mode the CMC bit must be set in the Physical Layer register and the SBC must be in Normal mode or Flash mode. In Active mode voltage regulator V2 is activated automatically. The CTC bit can be used to set the CAN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. After an overload condition on voltage regulator V2, the CTC bit must be cleared for reactivating the CAN transmitter. When leaving Active mode the CAN transmitter is disabled and the CAN receiver is monitoring the CAN-bus for a valid wake-up. The CAN termination is then working autonomously.
6.7.1.2
On-line mode In On-line mode the CAN bus pins and pin SPLIT (if enabled) are biased to the normal levels. The CAN transmitter is de-activated and RXDC reflects the CAN wake-up status. A CAN wake-up event is signalled to the microcontroller by clearing RXDC. If the bus stays continuously dominant or recessive for the Off-line time (toff-line), the Off-line state will be entered.
6.7.1.3
On-line Listen mode On-line Listen mode behaves similar to On-line mode, but all activity on the CAN-bus, with exception of a special global wake-up request, is ignored. The global wake-up request is described in Section 6.7.2. Pin RXDC is kept HIGH.
6.7.1.4
Off-line mode Off-line mode is the low power mode of the CAN transceiver. The CAN transceiver is disabled to save supply current and is high-ohmic terminated to ground. The CAN off-line time is programmable in two steps with the CAN Off-line Timer Control (COTC) bit. When entering On-line (Listen) mode from Off-line mode the CAN off-line time is temporarily extended to toff-line(ext).
6.7.2 CAN wake-up
To wake-up the UJA1065 via CAN it has to be distinguished between a conventional wake-up and a global wake-up in case partial networking is enabled (bit CPNC = 1). To pass the wake-up filter for a conventional wake-up a dominant, recessive, dominant, recessive signal on the CAN bus is needed; see Figure 9. For a global wake-up out of On-line Listen mode two distinct CAN data patterns are required:
* Initial message: C6 EE EE EE EE EE EE EF * Global wake-up message: C6 EE EE EE EE EE EE 37
The second pattern must be received within ttimeout after receiving the first pattern. Any CAN-ID can be used with these data patterns.
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If the CAN transceiver enters On-line Listen mode directly from Off-line mode the global wake-up message is sufficient to wake-up the SBC. This pattern must be received within ttimeout after entering On-line Listen mode. Should ttimeout elapse before receiving the global wake-up message, then both messages are required for a CAN wake-up.
CANH CANL
wake-up tCAN(dom1)
tCAN(reces)
tCAN(dom2)
001aad446
Fig 9. CAN wake-up timing diagram.
6.7.3 Termination control
In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated to 0.5 x VV2 via Ri. In Off-line mode CANH and CANL are terminated to GND via Ri. If V2 is disabled due to an overload condition both pins become floating.
6.7.4 Bus, RXD and TXD failure detection
The UJA1065 can distinguish between bus, RXD and TXD failures as indicated in Table 3. All failures are signalled separately in the CANFD bits in the System Diagnosis register. Any change (detection and recovery) forces an interrupt to the microcontroller, if this interrupt is enabled.
Table 3: Failure HxHIGH HxGND LxHIGH LxGND HxL Bus dom TXDC dom RXDC reces RXDC dom CAN-bus, RXD and TXD failure detection Description CANH short-circuit to VCC, VBAT14 or VBAT42 CANH short-circuit to GND CANL short-circuit to VCC, VBAT14 or VBAT42 CANL short-circuit to GND CANH short-circuit to CANL bus is continuously clamped dominant pin TXDC is continuously clamped dominant pin RXDC is continuously clamped recessive pin RXDC is continuously clamped dominant
6.7.4.1
TXDC dominant clamping If the TXDC pin is clamped dominant for longer than tTXDC(dom) the CAN transmitter is disabled. After the TXDC pin becomes recessive the transmitter is re-activated automatically when detecting bus activity or manually by setting and clearing the CTC bit.
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6.7.4.2
RXDC recessive clamping If the RXDC pin is clamped recessive while the CAN bus is dominant the CAN transmitter is disabled. The transmitter is re-activated automatically when RXDC becomes dominant or manually by setting and clearing the CTC bit.
6.7.5 GND shift detection
The SBC can detect ground shifts in reference to the CAN bus. Two different ground shift detection levels can be selected with the GSTHC bit in the Configuration register. The failure can be read out in the System Diagnosis register. Any detected or recovered GND shift event is signalled with an interrupt, if enabled.
6.8 LIN transceiver
The integrated LIN transceiver of the UJA1065 is a LIN 2.0 compliant transceiver. The transceiver has the following features:
* SAE J2602 compliant and compatible with LIN revision 1.3 * Fail-safe LIN termination to BAT42 via dedicated RTLIN pin * Enhanced error handling and reporting of bus and TXD failures; these failures are
separately identified in the System Diagnosis register
6.8.1 Mode control
The controller of the LIN transceiver provides two modes of operation: Active mode and Off-line mode; see Figure 10. In Off-line mode the transmitter and receiver do not consume current, but wake-up events will be recognized by the separate wake-up receiver.
Active mode
transmitter: ON/OFF (LTC) receiver: ON RXDL: bitstream RTLIN: ON/75 A
SBC enters Normal or Flash mode AND LMC = 1
SBC enters Stand-by, Start-up Restart or Fail-safe mode OR LMC = 0
Off-line mode
power-on transmitter: OFF receiver: wake-up RXDL: wake-up status RTLIN: 75 A/OFF SBC enters Fail-safe mode
001aad184
Fig 10. States LIN transceiver
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6.8.1.1
Active mode In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus. To enter Active mode the LMC bit must be set in the Physical Layer register and the SBC must be in Normal mode or Flash mode. The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. When leaving Active mode the LIN transmitter is disabled and the LIN receiver is monitoring the LIN-bus for a valid wake-up.
6.8.1.2
Off-line mode Off-line mode is the low power mode of the LIN transceiver. The LIN transceiver is disabled to save supply current. Pin RXDL reflects any wake-up event at the LIN-bus.
6.8.2 LIN wake-up
For a remote wake-up via LIN a LIN-bus signal is required as shown in Figure 11.
LIN
wake-up
tBUS(LIN)
001aad447
Fig 11. LIN wake-up timing diagram.
6.8.3 Termination control
The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 A; see Figure 12.
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Active mode and receiver dominant > t LIN(dom) OR Off-line mode
RTLIN = ON
supplied directly out of BAT42 Active mode and receiver recessive > t LIN(rec) OR mode change to Active mode
RTLIN = 75 A
supplied directly out of BAT42
Off-line mode AND receiver recessive > t LIN(rec)
mode change to Active mode
Off-line mode AND receiver dominant > t LIN(dom)
power-on
RTLIN = OFF
001aad183
Fig 12. States of the RTLIN pin
During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN provides an internal switch to BAT42. For master and slave operation an external resistor, 1 k or 30 k respectively, can be applied between pins RTLIN and LIN. An external diode in series with the termination resistor is not required due to the incorporated internal diode.
6.8.4 LIN driver capability
Setting the LDC bit in the Physical Layer Control register will increase the driver capability of the LIN output stage. This feature is used in auto-addressing systems, where the standard LIN 2.0 drive capability is insufficient.
6.8.5 Bus and TXDL failure detection
The SBC handles and reports the following LIN-bus related failures:
* LIN-bus shorted to ground * LIN-bus shorted to VBAT14 or VBAT42; the transmitter is disabled * TXDL clamped dominant; the transmitter is disabled
These failure events force an interrupt to the microcontroller whenever the status changes and the corresponding interrupt is enabled. 6.8.5.1 TXDL dominant clamping If the TXDL pin is clamped dominant for longer than tTXDL(dom) the LIN transmitter is disabled. After the TXDL pin becomes recessive the transmitter is re-activated automatically when detecting bus activity or manually by setting and clearing the LTC bit.
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6.8.5.2
LIN dominant clamping When the LIN-bus is clamped dominant for longer than tLIN(dom)(det) (which is longer than tTXDL(dom)), the state of the LIN termination is changed according to Figure 12.
6.8.5.3
LIN recessive clamping If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter is disabled. The transmitter is re-activated automatically when the LIN bus becomes dominant or manually by setting and clearing the LTC bit.
6.9 Inhibit and limp home output
The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for an extra (external) voltage regulator, or as a `limp home' output. The pin is controlled via the ILEN bit and ILC bit in the System Configuration register; see Figure 13.
state change via SPI OR enter Fail-safe mode
INH/LIMP: HIGH
ILEN = 1 ILC = 1 state change via SPI state change via SPI OR (enter Start-up mode after wake-up reset, external reset or V1 undervoltage) OR enter Restart mode OR enter Sleep mode state change via SPI
INH/LIMP: LOW
ILEN = 1 ILC = 0
state change via SPI OR enter Fail-safe mode
state change via SPI
INH/LIMP: floating
power-on ILEN = 0 ILC = 1/0
001aad178
Fig 13. States of the INH/LIMP pin
When pin INH/LIMP is used as inhibit output, a pull down resistor to GND ensures a default LOW level. The pin can be set to HIGH according to the state diagram. When pin INH/LIMP is used as limp home output, a pull up resistor to VBAT42 ensures a default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe mode.
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6.10 Wake-up input
The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are selected via the WAKE Sample Control bit (WSC):
* Continuous sampling (with an internal clock) if the bit is set * Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 14.
This is to save bias current within the external switches in low-power operation. Two repetition times are possible, 16 ms and 32 ms. If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the level of bit WSC. The dedicated status bits Edge WAKE Status (EWS) and Level WAKE Status (LWS) in the System Status register reflect the actual status of pin WAKE. The WAKE port can be disabled by clearing the WEN bit in the System Configuration register.
tw(CS) ton(CS) V3 approxemently 70 %
tsu(CS) sample active
VWAKE
signal already HIGH due to biasing (history)
button pushed
button released signal remains LOW due to biasing (history)
flip flop
VINTN
001aac307
Fig 14. Pin WAKE, cyclic sampling via V3
6.11 Interrupt output
Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in the Interrupt register is set. By reading the Interrupt register all bits are cleared. The Interrupt register will also be cleared during a system reset (RSTN LOW). As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN will be HIGH for at least tINTNH after each read-out of the Interrupt register. Without further interrupts within tINTNH pin INTN stays HIGH, otherwise it will revert to LOW again. To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal mode some interrupts are only allowed to occur once per watchdog period; see Section 6.13.7.
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If an interrupt is not read out within tRSTN(INT) a system reset is performed.
6.12 Temperature protection
The temperature of the SBC chip is monitored as long as the microcontroller voltage regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC, the temperature protection will not switch-off any part of the SBC or activate a defined system stop of its own accord. If the temperature is too high it generates an interrupt to the microcontroller, if enabled, and the corresponding status bit will be set. The microcontroller can then decide whether to switch-off parts of the SBC to decrease the chip temperature.
6.13 SPI interface
The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. The SPI uses four interface signals for synchronization and data transfer:
* * * *
SCS - SPI chip select; active LOW SCK - SPI clock; default level is LOW due to low-power concept SDI - SPI data input SDO - SPI data output; floating when pin SCS is HIGH
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge; see Figure 15.
SCS
SCK
01 sampled
02
03
04
15
16
SDI
X
MSB
14
13
12
01
LSB
X
SDO
floating
X
MSB
14
13
12
01
LSB
floating
mce634
Fig 15. SPI timing protocol
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To protect against wrong or illegal SPI instructions, the SBC detects the following SPI failures:
* SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC. In Start-up and Restart mode a reset is forced instead of an interrupt
* Unallowed mode changes according to Figure 3 result in an immediate system reset * Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see Section 6.13.3
6.13.1 SPI register mapping
Any control bit which can be set by software is readable by the application. This allows software debugging as well as control algorithms to be implemented. Watchdog serving and mode setting is performed within the same access cycle; this only allows an SBC mode change whilst serving the watchdog. Each register carries 12 data bits; the other 4 bits are used for register selection and read/write definition.
6.13.2 Register overview
The SPI interface gives access to all SBC registers; see Table 4. The first two bits (A1 and A0) of the message header define the register address, the third bit is the read register select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO) allows `read only' access to one of the feedback registers. Which of the SBC registers can be accessed also depends on the SBC operating mode.
Table 4: Register overview Operating mode all modes Normal mode; Standby mode; Flash mode Start-up mode; Restart mode 10 Normal mode; Standby mode Start-up mode; Restart mode; Flash mode 11 Normal mode; Standby mode Start-up mode; Restart mode; Flash mode Write access (RO = 0) Read access (RO = 0 or RO = 1) Read Register Select (RRS) bit = 0 Mode register Interrupt Enable register System Status register Interrupt Enable Feedback register Interrupt Enable Feedback register System Configuration Feedback register System Configuration Feedback register Physical Layer Control Feedback register Physical Layer Control Feedback register Read Register Select (RRS) bit = 1 System Diagnosis register Interrupt register
Register address bits (A1, A0) 00 01
Special Mode register System Configuration register General Purpose register 0
Special Mode Feedback register General Purpose Feedback register 0 General Purpose Feedback register 0 General Purpose Feedback register 1 General Purpose Feedback register 1
Physical Layer Control register General Purpose register 1
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6.13.3 Mode register
In the Mode register the watchdog is defined and re-triggered, and the SBC operating mode is selected. The Mode register also contains the global enable output bit (EN) and the Software Development Mode (SDM) control bit. During system operation cyclic access to the Mode register is required to serve the watchdog. This register can be written to in all modes. At system start-up the Mode register must be written to within tWD(init) from releasing RSTN (HIGH-level on RSTN). Any write access is checked for proper watchdog and system mode coding. If an illegal code is detected, access is ignored by the SBC and a system reset is forced in accordance with the state diagram of the system controller; see Figure 3.
Table 5: Bit 15 and 14 13 12 11 to 6 5 to 3 Mode register bit description (bits 15 to 12 and 5 to 0) Symbol A1, A0 RRS RO NWP[5:0] OM[2:0] Description register address Read Register Select Read Only see Table 6 Operating Mode 001 010 011 100 101 110 111 2 SDM Software Development Mode Enable reserved 1 0 1 0 0 0 Normal mode Standby mode initialize Flash mode [1] Sleep mode initialize Normal mode leave Flash mode Flash mode
[1]
Value 00 1 0 1 0
Function select Mode register read System Diagnosis register read System Status register read selected register without writing to Mode register read selected register and write to Mode register
Software Development Mode enabled [2] Normal watchdog, interrupt, reset monitoring and fail-safe behavior EN output pin HIGH EN output pin LOW reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit
1
EN
[1]
Flash mode can be entered only with the watchdog service sequence `Normal mode to Flash mode to Normal mode to Flash mode', while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up mode to prepare the Cfor flash memory download. The four RSS bits in the System Status register reflect the reset source information, confirming the Flash entry sequence. By using the Initializing Flash mode (within tWD(init) after system reset) the SBC will now successfully enter Flash mode. See Section 6.14.1.
[2]
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[1]
Table 6: Bit
Mode register bit description (bits 11 to 6) Symbol Description Value
Time Normal mode (ms) Standby mode (ms) 20 40 80 160 320 640 1024 2048 4096 OFF [2] 30 60 120 240 480 960 1536 3072 6144 OFF [2] 50 100 200 400 800 1600 1560 5120 10240 OFF [2] Flash mode (ms) 20 40 80 160 320 640 1024 2048 4096 8192 30 60 120 240 480 960 1536 3072 6144 12288 50 100 200 400 800 1600 1560 5120 10240 20480 Sleep mode (ms) 160 320 640 1024 2048 3072 4096 6144 8192 OFF [3] 240 480 960 1536 3072 4608 6144 9216 12288 OFF [3] 400 800 1600 2560 5120 7680 10240 15360 20480 OFF [3]
11 to 6
NWP[5:0]
00 1001 Nominal Watchdog Period 00 1100 WDPRE = 00 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110 Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 01 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110 Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 10 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 10 0100 10 1101 11 0011 11 0101 11 0110
4 8 16 32 40 48 56 64 72 80 6 12 24 48 60 72 84 96 108 120 10 20 40 80 100 120 140 160 180 200
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Table 6: Bit
Mode register bit description (bits 11 to 6) ...continued [1] Symbol Description Value Time Normal mode (ms) Standby mode (ms) 70 140 280 560 1120 2240 3584 7168 14336 OFF [2] Flash mode (ms) 70 140 280 560 1120 2240 3584 7168 14336 28672 Sleep mode (ms) 560 1120 2240 3584 7168 10752 14336 21504 28672 OFF [3]
11 to 6
NWP[5:0]
001001 Nominal Watchdog Period 001100 WDPRE = 11 (as 010010 set in the Special 010100 Mode register) 011011 100100 101101 110011 110101 110110
14 28 56 112 140 168 196 244 252 280
[1] [2] [3]
The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for fosc = 512 kHz. See Section 6.4.4. The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry without dips on V1. See Section 6.4.4.
6.13.4 System status register
This register allows status information to be read back from the SBC. This register can be read in all modes.
Table 7: Bit 15 and 14 13 12 System status register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 00 0 1 0 read System Status register without writing to Mode register read System Status register and write to Mode register Function read System Status register
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Table 7: Bit 11 to 8
System status register bit description ...continued Symbol RSS[3:0] Description Reset Source [1] Value 0000 Function Power-on reset; first connection of BAT42 or BAT42 below power-on voltage threshold or RSTN was forced LOW externally cyclic wake-up out of Sleep mode low V1 supply; V1 has dropped below the selected reset threshold V1 current above threshold within Standby mode while watchdog OFF behavior and reset option (V1CMC bit) are selected V3 voltage is down due to overload occurring during Sleep mode SBC successfully left Flash mode SBC ready to enter Flash mode CAN wake-up event LIN wake-up event local wake-up event (via pin WAKE) wake-up out of Fail-safe mode watchdog overflow watchdog not initialized in time; tWD(init) exceeded watchdog triggered too early; window missed illegal SPI access interrupt not served within tRSTN(INT) CAN wake-up detected; cleared upon read no CAN wake-up LIN wake-up detected; cleared upon read no LIN wake-up pin WAKE negative edge detected; cleared upon read pin WAKE no edge detected pin WAKE above threshold pin WAKE below threshold chip temperature exceeds the warning limit chip temperature is below the warning limit Software Development mode on Software Development mode off pin EN output activated (V1-related HIGH level) pin EN output released (LOW level) Power-on reset; cleared after a successfully entered Normal mode No Power-on reset
0001 0010 0011
0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7 6 5 4 3 2 1 0 CWS LWS EWS WLS TWS SDMS ENS PWONS CAN Wake-up Status LIN Wake-up Status Edge Wake Status Wake Level Status Temperature Warning Status Software Development Mode Status Enable status Power-on reset Status 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
[1]
The RSS bits are updated with each reset event and not cleared. The last reset event is captured.
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6.13.5 System diagnosis register
This register allows diagnosis information to be read back from the SBC. This register can be read in all modes.
Table 8: Bit 15 and 14 13 12 System diagnosis register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 00 1 1 0 11 10 to 7 GSD CANFD [3:0] Ground Shift Diagnosis CAN failure diagnosis 1 0 1111 1110 1100 1101 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 6 and 5 LINFD[1:0] LIN failure diagnosis 11 10 01 00 4 3 2 V3D V2D V1D V3 diagnosis V2 diagnosis V1 diagnosis 1 0 1 0 1 0 read System Diagnosis register without writing to Mode register read System Diagnosis register and write to Mode register system GND shift is outside selected threshold system GND shift is within selected threshold pin TXDC is continuously clamped dominant pin RXDC is continuously clamped dominant the bus is continuously clamped dominant pin RXDC is continuously clamped recessive reserved reserved pin CANH is shorted to pin CANL pin CANL is shorted to VCC, VBAT14 or VBAT42 reserved CANH is shorted to GND CANL is shorted to GND CANH is shorted to VCC, VBAT14 or VBAT42 reserved reserved reserved no failure TXDL is clamped dominant or shorted to RXDL LIN is shorted to GND (dominant clamped) LIN is shorted to VBAT (recessive clamped) no failure OK fail; V3 is disabled due to an overload situation OK [1] fail; V2 is disabled due to an overload situation OK; V1 always above VUV(VFI) since last read access fail; V1 was below VUV(VFI) since last read access; bit is set again with read access Function read System Diagnosis register
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Table 8: Bit 1 and 0
System diagnosis register bit description ...continued Symbol CANMD [1:0] Description CAN Mode Diagnosis Value 11 10 01 00 Function CAN is in Active mode CAN is in On-line mode CAN is in On-line Listen mode CAN is in Off-line mode, or V2 is not active
[1]
V2D will be set when V2 is reactivated after a failure. See Section 6.6.3.2.
6.13.6 Interrupt enable register and interrupt enable feedback register
These registers allow setting, clearing and reading back the interrupt enable bits of the SBC.
Table 9: Bit 15 and 14 13 12 Interrupt enable and interrupt enable feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 1 0 1 0 11 WTIE Watchdog Time-out Interrupt Enable [1] 1 Function select the Interrupt Enable register read the Interrupt register read the Interrupt Enable Feedback register read the register selected by RRS without writing to Interrupt Enable register read the register selected by RRS and write to Interrupt Enable register a watchdog overflow during Standby causes an interrupt instead of a reset event (interrupt based cyclic wake-up feature) no interrupt forced on watchdog overflow; a reset is forced instead exceeding or dropping below the temperature warning limit causes an interrupt no interrupt forced exceeding or dropping below the GND shift limit causes an interrupt no interrupt forced wrong number of CLK cycles (more than, or less than 16) forces an interrupt; from Start-up mode and Restart mode a reset is performed instead of an interrupt no interrupt forced; SPI access is ignored if the number of cycles does not equal 16 falling edge at SENSE forces an interrupt no interrupt forced clearing of V1D, V2D or V3D forces an interrupt no interrupt forced any change of the CAN Failure status bits forces an interrupt no interrupt forced any change of the LIN Failure status bits forces an interrupt no interrupt forced
0 10 OTIE Over-Temperature Interrupt Enable Ground Shift Interrupt Enable SPI clock count Failure Interrupt Enable 1 0 9 GSIE 1 0 8 SPIFIE 1
0 7 6 5 BATFIE VFIE CANFIE BAT Failure Interrupt Enable 1 0
Voltage Failure Interrupt 1 Enable 0 CAN Failure Interrupt Enable LIN Failure Interrupt Enable 1 0
4
LINFIE
1 0
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Table 9: Bit 3
Interrupt enable and interrupt enable feedback register bit description ...continued Symbol WIE Description WAKE Interrupt Enable [2] Value 1 0 Function a negative edge at pin WAKE generates an interrupt in Normal mode, Flash mode or Standby mode a negative edge at pin WAKE generates a reset in Standby mode; No interrupt in any other mode a watchdog restart during watchdog OFF generates an interrupt no interrupt forced CAN-bus event results in a wake-up interrupt in Standby mode CAN-bus event results in a reset in Standby mode; No interrupt in any other mode LIN-bus event results in a wake-up interrupt in Standby mode LIN-bus event results in a reset in Standby mode; No interrupt in any other mode
2
WDRIE
Watchdog Restart Interrupt Enable CAN Interrupt Enable
1 0
1
CANIE
1 0
0
LINIE
LIN Interrupt Enable
1 0
[1] [2]
This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required (fail-safe behavior). WEN (in the SC register) has to be set to activate the WAKE port function globally.
6.13.7 Interrupt register
The Interrupt register allows the cause of an interrupt event to be read. The register is cleared upon a read access and upon any reset event. Hardware ensures that no interrupt event is lost in case there is a new interrupt forced while reading the register. After reading the Interrupt register pin INTN is released for tINTNH to guarantee an edge event at pin INTN. The interrupts can be classified into two groups:
* Timing critical interrupts which require immediate reaction (SPI clock count failure
which needs a new SPI command to be resent immediately, and a BAT failure which needs critical data to be saved immediately into the non-volatile memory)
* Interrupts which do not require an immediate reaction (OVERTEMP, Ground Shift,
CAN and LIN failures, V1, V2 and V3 failures and the wake-ups via CAN, LIN and WAKE. These interrupts will be signalled in Normal mode to the microcontroller once per watchdog period (maximum); this prevents overloading the microcontroller with unexpected interrupt events (e.g. a chattering CAN failure). However, these interrupts are reflected in the interrupt register
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Table 10: Bit 15 and 14 13 12
Interrupt register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 1 1 0 read the Interrupt register without writing to the Interrupt Enable register read the Interrupt register and write to the Interrupt Enable register a watchdog overflow during Standby mode has caused an interrupt (interrupt-based cyclic wake-up feature) no interrupt the temperature warning status (TWS) has changed no interrupt the ground shift diagnosis bit (GSD) has changed no interrupt wrong number of CLK cycles (more than, or less than 16) during SPI access no interrupt; SPI access is ignored if the number of CLK cycles does not equal 16 falling edge at pin SENSE has forced an interrupt no interrupt V1D, V2D or V3D has been cleared no interrupt CAN failure status has changed no interrupt LIN failure status has changed no interrupt a negative edge at WAKE has been detected no interrupt A watchdog restart during watchdog OFF has caused an interrupt no interrupt CAN wake-up event has caused an interrupt no interrupt LIN wake-up event has caused an interrupt no interrupt Function read Interrupt register
11
WTI
Watchdog Time-out Interrupt OverTemperature Interrupt Ground Shift Interrupt SPI clock count Failure Interrupt
1 0
10 9 8
OTI GSI SPIFI
1 0 1 0 1 0
7 6 5 4 3 2
BATFI VFI CANFI LINFI WI WDRI
BAT Failure Interrupt
1 0
Voltage Failure Interrupt 1 0 CAN Failure Interrupt LIN Failure Interrupt Wake-up Interrupt Watchdog Restart Interrupt CAN Wake-up Interrupt LIN Wake-up Interrupt 1 0 1 0 1 0 1 0
1 0
CANI LINI
1 0 1 0
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6.13.8 System configuration register and system configuration feedback register
These registers allow configuration of the behavior of the SBC, and allow the settings to be read back.
Table 11: Bit 15 and 14 13 12 System configuration and system configuration feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 10 1 0 1 0 11 and 10 9 8 7 and 6 GSTHC RLC V3C[1:0] reserved GND Shift Threshold Control Reset Length Control V3 Control 0 1 0 1 [1] 0 11 10 01 00 5 4 V1CMC reserved V1 Current Monitor Control 0 1 0 3 2 1 0 WEN WSC ILEN ILC WAKE Enable [2] WAKE Sample Control INH/LIMP Enable INH/LIMP Control 1 0 1 0 1 0 1 0
[1] [2]
Function select System Configuration register read the General Purpose Feedback register 0 read the System Configuration Feedback register read register selected by RRS without writing to System Configuration register read register selected by RRS and write to System Configuration register reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit Vth(GSD)(cm) widened threshold Vth(GSD)(cm) normal threshold tRSTNL long reset lengthening time selected tRSTNL short reset lengthening time selected Cyclic mode 2; tw(CS) long period; see Figure 14 Cyclic mode 1; tw(CS) short period; see Figure 14 continuously ON OFF reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit an increasing V1 current causes a reset if the watchdog was disabled during Standby mode an increasing V1 current just reactivates the watchdog during Standby mode, and an interrupt is forced (if enabled) WAKE pin enabled WAKE pin disabled WAKE mode cyclic sample WAKE mode continuous sample INH/LIMP pin active (See ILC bit) INH/LIMP pin floating INH/LIMP pin HIGH if ILEN bit is set INH/LIMP pin LOW if ILEN bit is set
RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached. If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and LWS within the System Status register.
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6.13.9 Physical layer control register and physical layer control feedback register
These registers allow configuration of the CAN transceiver and LIN transceiver of the SBC and allow the settings to be read back.
Table 12: Bit 15 and 14 13 12 Physical layer control and physical layer control feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 11 1 0 1 0 11 10 V2C CPNC V2 Control 0 1 CAN Partial Networking 1 Control 0 9 8 7 COTC CTC CRC CAN Off-line Time Control [1] CAN Transmitter Control [2] CAN Receiver Control 1 0 1 0 1 0 6 5 4 3 2 1 0 CMC CSC LMC LSC LDC LWEN LTC CAN Mode Control CAN Split Control LIN Mode Control LIN Slope Control LIN Driver Control LIN Wake-up Enable LIN Transmitter Control 1 0 1 0 1 0 1 0 1 0 1 0 1 0
[1] [2]
Function select Physical Layer Control register read the General Purpose Feedback register 1 read the Physical Layer Control Feedback register read the register selected by RRS without writing to the Physical Layer Control register read the register selected by RRS and write to Physical Layer Control register V2 remains active in CAN Off-line mode V2 is OFF in CAN Off-line mode CAN transceiver enters On-line Listen mode instead of On-line mode; cleared whenever the SBC enters On-line mode or Active mode On-line Listen mode disabled toff-line long period (extended to toff-line(ext) after wake-up) toff-line short period (extended to toff-line(ext) after wake-up) CAN transmitter is disabled CAN transmitter is enabled TXD signal is forwarded directly to RXD for self-test purposes (loopback behavior); only if CTC = 1 TXD signal is not forwarded to RXD (normal behavior) CAN Active mode (in Normal mode and Flash mode only) CAN Active mode disabled CAN SPLIT pin active CAN SPLIT pin floating LIN Active mode (in Normal mode and Flash mode only) LIN Active mode disabled up to 10 kbit/s (low slope) up to 20 kbit/s (normal) increased LIN driver current capability LIN driver in conformance with the LIN 2.0 standard Wake-up via the LIN-bus enabled Wake-up via the LIN-bus disabled LIN transmitter is disabled LIN transmitter is enabled
For the CAN transceiver to enter Off-Line mode from On-line or On-line Listen mode a minimum time without bus activity is needed. This minimum time toff-line is defined by COTC; see Section 6.7.1.4. In case of an RXDC / TXDC interfacing failure the CAN transmitter is disabled without setting CTC. Recovery from such a failure is automatic when CAN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing the CTC bit under software control.
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6.13.10 Special mode register and special mode feedback register
These registers allow configuration of global SBC parameters during start-up of a system, and allow the settings to be read back.
Table 13: Bit 15 and 14 13 12 Special mode register and special mode feedback register bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 01 0 1 1 0 11 and 10 9 ISDM reserved Initialize Software Development Mode [1] Error-pin Emulation Mode 0 1 0 1 Function select Special Mode register read the Special Mode Feedback register read the Interrupt Feedback register read the register selected by RRS without writing to the Special Mode register read the register selected by RRS and write to the Special Mode register reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit initialization of Software Development mode normal watchdog interrupt, reset monitoring and fail-safe behavior pin EN reflects the status of the CANFD bits: EN is set if CANFD = 0000 (no error) EN is cleared if CANFD is not 0000 (error) 0 7 6 and 5 WDPRE [1:0] reserved Watchdog Prescaler 0 00 01 10 11 4 and 3 V1RTHC [1:0] V1 Reset Threshold Control 11 10 01 00 2 to 0 reserved 0 pin EN behaves as an enable pin; see Section 6.5.2 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit watchdog prescale factor 1 watchdog prescale factor 1.5 watchdog prescale factor 2.5 watchdog prescale factor 3.5 V1 reset threshold = 0.9 x VV1(nom) V1 reset threshold = 0.7 x VV1(nom) [2] V1 reset threshold = 0.8 x VV1(nom) [3] V1 reset threshold = 0.9 x VV1(nom) reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit
8
ERREM
[1] [2] [3]
See Section 6.14.1. Not supported for the 3V0 and 3V3 version. Not supported for the 3V0 version.
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6.13.11 General purpose registers and general purpose feedback registers
The UJA1065 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis, or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a `Device Identification Code' consisting of the SBC type and SBC version. This code is available until it is overwritten by the microcontroller (as indicated by the DIC bit).
Table 14: Bit 15, 14 13 12 General purpose register 0 and general purpose feedback register 0 bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 10 1 0 1 0 11 DIC Device Identification Control [1] General Purpose bits [2] 1 0 1 0
[1] [2]
Function read the General Purpose Feedback register 0 read the General Purpose Feedback register 0 read the System Configuration Feedback register read the register selected by RRS without writing to the General Purpose register 0 read the register selected by RRS and write to the General Purpose register 0 General Purpose register 0 contains user defined bits General Purpose register 0 contains the Device Identification Code user defined user defined
10 to 0
GP0[10:0]
The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC. During power-up the General Purpose register 0 is loaded with a `Device Identification Code' consisting of the SBC type and SBC version, and the DIC bit is cleared.
Table 15: Bit 15 and 14 13 12
General purpose register 1 and general purpose feedback register 1 bit description Symbol A1, A0 RRS RO Description register address Read Register Select Read Only Value 11 1 0 1 0 Function select General Purpose register 1 read the General Purpose Feedback register 1 read the Physical Layer Control Feedback register read the register selected by RRS without writing to the General Purpose register 1 read the register selected by RRS and write to the General Purpose register the relevant General Purpose bit has been set the relevant General Purpose bit has been cleared
11 to 0
GP1[11:0]
General Purpose bits
1 0
6.13.12 Register configurations at reset
At Power-on, Start-up and Restart the setting of the SBC registers is predefined. With external reset events (edge at pin RSTN) the registers will be set as in Start-up mode, with the exception of the ILEN bit in the System Configuration register.
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Table 16: Symbol RSS CWS
System status register: status at reset Name Reset Source Status CAN Wake Status Power-on 0000 (Power-on reset) 0 (no CAN wake-up) Start-up
[1]
Restart
[1]
any value except 1100
0000 or 0010 or 1100 or 1110
1 if reset is caused by a no change CAN wake-up, otherwise no change 1 if reset is caused by a no change LIN wake-up, otherwise no change 1 if reset is caused by a no change wake-up via pin WAKE, otherwise no change actual status actual status actual status 0 (EN = LOW) no change actual status actual status actual status 0 (EN = LOW) no change
LWS
LIN Wake Status
0 (no LIN wake-up)
EWS
Edge Wake Status
0 (no edge detected)
WLS TWS SDMS ENS PWONS
[1] Depends on history.
Wake Level Status Temperature Warning Status
actual status 0 (no warning)
Software Development actual status Mode Status Enable Status Power-on Status 0 (EN = LOW) 1 (Power-on reset)
Table 17: Symbol GSD CANFD LINFD V3D V2D V1D CANMD Table 18: Symbol all Table 19: Symbol all
System diagnosis register: status at reset Name Power-on Start-up actual status actual status actual status actual status actual status actual status actual status Restart actual status actual status actual status actual status actual status actual status actual status Ground Shift Diagnosis 0 (OK) CAN Failure Diagnosis 0000 (no failure) LIN Failure Diagnosis V3 Diagnosis V2 Diagnosis V1 Diagnosis CAN Mode Diagnosis 00 (no failure) 1 (OK) 1 (OK) actual status 00 (Off-line)
Interrupt enable register and interrupt enable feedback register: status at reset Name all bits Interrupt register: status at reset Name all bits Power-on 0 (no interrupt) Start-up 0 (no interrupt) Restart 0 (no interrupt) Power-on 0 (interrupt disabled) Start-up no change Restart no change
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Table 20: Symbol GSTHC RLC V3C V1CMC WEN WSC ILEN
System configuration register and system configuration feedback register: status at reset Name GND Shift level Threshold Control Reset Length Control V3 Control Power-on 0 (normal) 0 (short) 00 (off) Start-up no change no change no change no change no change no change see Figure 13 if ILC = 1, otherwise no change no change Restart no change 1 (long) no change no change no change no change 0 (floating) if ILC = 1, otherwise no change no change Fail-Safe no change 1 (long) no change no change no change no change 1 (active)
V1 Current Monitor 0 (WD restart) Control Wake Enable Wake Sample Control INH/LIMP Enable 1 (enabled) 0 (control) 0 (floating)
ILC Table 21: Symbol V2C CPNC
INH/LIMP Control
0 (LOW)
0 (LOW)
Physical layer control register and physical layer control feedback register: status at reset Name V2 Control Power-on 0 (auto) Start-up no change Restart no change Fail-Safe 0 (auto) 0 (On-line Listen mode disabled)
CAN Partial 0 (On-line Listen Networking Control mode disabled)
0 if reset is caused no change by a CAN wake-up, otherwise no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change
COTC CTC CRC CMC CSC LMC LSC LDC LWEN LTC
CAN Off-line Time Control CAN Transmitter Control CAN Receiver Control
1 (long) 0 (on) 0 (normal)
no change no change no change no change no change no change no change no change no change no change
CAN Mode Control 0 (Active mode disabled) CAN Split Control LIN Mode Control LIN Slope Control LIN Driver Control LIN Wake-up Enable LIN Transmitter Control 0 (off) 0 (Active mode disabled) 0 (normal) 0 (LIN 2.0) 1 (enabled) 0 (on)
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Table 22: Symbol ISDM ERREM WDPRE V1RTHC Table 23: Symbol DIC GP0[10:7] GP0[6:0]
Special mode register: status at reset Name Initialize Software Development Mode Error pin emulation mode Watchdog Prescale Factor V1 Reset Threshold Control Power-on 0 (no) 0 (EN function) 00 (factor 1) 00 (90 %) Start-up no change no change no change no change Restart no change no change no change 00 (90 %)
General purpose register 0 and general purpose feedback register 0: status at reset Name Device Identification Control general purpose bits 10 to 7 (version) general purpose bits 6 to 0 (SBC type) Power-on 0 (Device ID) Mask version 000 0101 (UJA1065) Start-up no change no change no change Restart no change no change no change
Table 24: Symbol GP1[11:0]
General purpose register 1 and general purpose feedback register 1: status at reset Name general purpose bits 11 to 0 Power-on 0000 0000 0000 Start-up no change Restart no change
6.14 Test modes
6.14.1 Software Development mode
The Software Development mode is intended to support software developers in writing and pre-testing application software without having to work around watchdog triggering and without unwanted jumps to Fail-safe mode. In Software Development mode the following events do not force of a system reset:
* * * *
Watchdog overflow in Normal mode Watchdog window miss Interrupt time-out Elapsed start-up time
However, the reset source information is still provided in the System Status register as if there was a real reset event. The exclusion of watchdog related resets allows simplified software testing, because possible problems in the watchdog triggering can be indicated by interrupts instead of resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode. This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode of the SBC. All transitions to Fail-safe mode are disabled. This allows working with an external emulator that clamps the reset line LOW in debugging mode. A V1 under voltage of more than tV1(CLT) is the only exception that results in entering Fail-safe mode (to protect the SBC). Transitions from Start-up mode to Restart mode are still possible.
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There are two possibilities to enter Software Development mode. One is by setting the ISDM bit via the Special Mode register; possible only once after a first battery connection while the SBC is in Start-up mode. The second possibility to enter Software Development mode is by applying a 7 V to 7.5 V input voltage at pin TEST before the battery is applied to pin BAT42. To stay in Software Development mode the SDM bit in the Mode register has to be set with each Mode register access (i.e. Watchdog triggering) regardless of how Software Development mode was entered. The Software Development mode can be exited at any time by clearing the SDM bit in the Mode register. Re-entering the Software Development mode is only possible by reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.
6.14.2 Forced Normal mode
For system evaluation purposes the UJA1065 offers the Forced Normal mode. This mode is strictly for evaluation purposes only. In this mode the characteristics as defined in Section 8 and Section 9 cannot be guaranteed. In Forced normal mode the SBC behaves as follows:
* * * * * *
SPI access (writing and reading) is blocked Watchdog disabled Interrupt monitoring disabled Reset monitoring disabled Reset lengthening disabled All transitions to Fail-safe mode are disabled, except a V1 under voltage for more than 256 ms under voltage, a reset is performed until V1 is restored (normal behavior), and the SBC stays in Forced Normal mode; in case of a continuous overload at V1 (> 256 ms) Fail-safe mode is entered
* V1 is started with the defined reset (20 ms LOW-to-HIGH transition) In case of a V1
* * * * * *
V2 is on; overload protection active V3 is on; overload protection active CAN and LIN are in Active mode and cannot switch to Off-line mode INH/LIMP pin is HIGH SYSINH is HIGH EN pin at same level as RSTN pin
Forced Normal mode is activated by applying a stable 12 V to 12.5 V input voltage at the TEST pin during first battery connection.
9397 750 14409
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Objective data sheet
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Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
7. Limiting values
Table 25: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol VBAT42 VBAT14 VDC(n) Parameter BAT42 supply voltage load dump; t 500 ms BAT14 supply voltage load dump; t 500 ms DC voltages on pins TXDC, RXDC, TXDL, RXDL, RSTN, INTN, SDO, SDI, SCK, SCS and EN INH/LIMP, V3, SYSINH and WAKE CANH, CANL, SPLIT and LIN Vtrt VRTLIN VV1, VV2 VSENSE VTEST Tstg Tamb Tvj Vesd transient voltage at pins CANH, CANL and LIN DC voltage at pin RTLIN DC voltage at pins V1 and V2 DC voltage at pin SENSE DC voltage at pin TEST storage temperature ambient temperature virtual junction temperature electrostatic discharge voltage HBM at pins CANH, CANL, SPLIT, LIN, RTLIN, WAKE, BAT42, V3, SENSE; with respect to GND at any other pin MM; at any pin
[1]
[3] [1] [2]
Conditions
Min -0.3 -0.3 -0.3 -1.5 -60
Max +60 +60 +33 +48 VV1 + 0.3 VBAT42 + 0.3 +60 +100 VBAT42 + 1.2 +5.5 VBAT42 + 1.2 +15 +150 +125 +150 +8.0
Unit V V V V V V V V V V V V C C C kV
in accordance with ISO 7637
-150 -60 -0.3 -0.3 -0.3 -55 -40 -40 -8.0
-2.0 -200
+2.0 +200
kV V
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature Tvj is: Tvj = Tamb + Pd x Rth(vj-amb), where Rth(vj-amb) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (Pd) and ambient temperature (Tamb). Human Body Model (HBM): C = 100 pF; R = 1.5 k. Machine Model (MM): C = 200 pF; L = 0.75 H; R = 10 .
[2] [3]
9397 750 14409
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Objective data sheet
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Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
8. Static characteristics
Table 26: Characteristics Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol IBAT42 Parameter Conditions Min Typ 55 Max 95 Unit A Supply; pin BAT42 BAT42 supply current V1, V2 off; V3 off; CAN and LIN in Off-line mode; OTIE = BATFIE = 0; ISYSINH = IWAKE = IRTLIN = ILIN = 0 mA additional BAT42 supply current V1 and / or V2 on; ISYSINH = 0 mA V3 in cyclic mode; IV3 = 0 mA V3 continuously on; IV3 = 0 mA Tvj warning enabled; OTIE = 1 SENSE enabled; BATFIE = 1 CAN in Active mode; CMC = 1 LIN in Active mode; LMC = 1; VTXDL = VV1; IRTLIN = ILIN = 0 mA LIN in Active mode; LMC = 1; VTXDL = 0 V (t < tLIN(dom)); IRTLIN = ILIN = 0 mA; VBAT42 = 12 V LIN in Active mode; LMC = 1; VTXDL = 0 V (t < tLIN(dom)); IRTLIN = ILIN = 0 mA; VBAT42 = 27 V VPOR(BAT42) BAT42 voltage level for Power-on reset status bit change for setting PWONS PWONS = 0; VBAT42 falling for clearing PWONS PWONS = 1; VBAT42 rising Supply; pin BAT14 IBAT14 BAT14 supply current V1 and V2 off; CAN and LIN in Off-line mode; ILEN =CSC = 0; IINH/LIMP = ISPLIT = 0 mA 2 5 A 5 5.5 V 4.5 5 V
IBAT42(add)
-
53 0 30 20 2 750 650
76 1 50 40 5 1500 1300
A A A A A A A
-
1.5
5
mA
-
3
10
mA
9397 750 14409
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Objective data sheet
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Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol IBAT14(add) Parameter additional BAT14 supply current Conditions V1 on; IV1 = 0 mA V2 on; IV2 = 0 mA INH/LIMP enabled; ILEN = 1; IINH/LIMP = 0 mA CAN in Active mode; CMC = 1; ICANH = ICANL = 0 mA SPLIT active; CSC = 1; ISPLIT = 0 mA VBAT14 BAT14 voltage level for normal output current capability at V1 BAT14 voltage level for high output current capability at V1 Battery supply monitor input; pin SENSE Vth(SENSE) IIH(SENSE) input threshold low battery voltage HIGH-level input current Normal mode; BATFIE = 1 Standby mode; BATFIE = 1 Normal mode or Standby mode; BATFIE = 0 Voltage source; pin V1 [1] Vo(V1) output voltage VBAT14 = 9 V to 16 V; IV1 = -50 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -5 mA; Tj = 25 C VV1 supply voltage regulation load regulation VBAT14 = 9 V to 16 V; IV1 = -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -50 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV1 = -5 mA; Tj = -40 C to +150 C VBAT14 = 14 V; V1RTHC = 00 or 11 VBAT14 = 14 V; V1RTHC = 01 VBAT14 = 14 V; V1RTHC = 10
[2]
Min -
Typ 200 200 1 5
Max 300 300 2 10
Unit A A A mA
9
1 -
2 27
mA V
6
-
8
V
1
2.5 50 10 0
4 1
V A A A
VV1(nom) - 0.1 VV1(nom) - 0.025 -
VV1(nom)
VV1(nom) + 0.1 VV1(nom) + 0.025 25 25
V
VV1(nom)
V mV mV
voltage drift with temperature Vdet(UV)(V1) undervoltage detection and reset activation level
0.90 x VV1(nom) 0.80 x VV1(nom) 0.70 x VV1(nom)
0.92 x VV1(nom) 0.82 x VV1(nom) 0.72 x VV1(nom)
200 0.94 x VV1(nom) 0.84 x VV1(nom) 0.74 x VV1(nom)
ppm/K V V V
9397 750 14409
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Objective data sheet
Rev. 01 -- 10 August 2005
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Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol VUV(VFI) Parameter Conditions Min 0.90 x VV1(nom) -2 Typ 0.92 x VV1(nom) -5 Max 0.94 x VV1(nom) -10 Unit V undervoltage level for VBAT14 = 14 V; VFIE = 1 generating a VFI interrupt undercurrent threshold for watchdog enable undercurrent threshold for watchdog disable output current capability VBAT14 = 9 V to 27 V; VV1 = 0.06 x VV1(nom) VBAT14 = 9 V to 27 V; V1 shorted to GND VBAT14 = 6 V to 8 V; VV1 = 0.06 x VV1(nom) VBAT14 = 5.5 V; VV1 = 0.06 x VV1(nom) VBAT14 = 5.5 V; VV1 = 0.16 x VV1(nom) Zds(on) regulator impedance between pins BAT14 and V1 output voltage VBAT14 = 4 V to 5 V
IthH(V1)
mA
IthL(V1)
-1.5
-3
-5
mA
IV1
-120 -250 -150 -250 -
-135 -110 -400 -250 -400 4
-200 8
mA mA mA mA mA
Voltage source; pin V2 [3] Vo(V2) VBAT14 = 9 V to 16 V; IV2 = -50 mA to -5 mA VBAT14 = 14 V; IV2 = -10 mA; Tj = 25 C VV2 supply voltage regulation load regulation VBAT14 = 9 V to 16 V; IV2 = -10 mA; Tj = 25 C VBAT14 = 14 V; IV2 = -50 mA to -5 mA; Tj = 25 C VBAT14 = 14 V; IV2 = -10 mA; -40 C < Tj < 150 C VBAT14 = 9 V to 27 V; VV2 = 300 mV VBAT14 = 9 V to 27 V; V2 shorted to GND VBAT14 = 6 V to 8 V; VV2 = 300 mV VBAT14 = 5.5 V; VV2 = 300 mV
[2]
4.8 4.95 -
5.0 5.0
5.2 5.05 25 50
V V mV mV
voltage drift with temperature IV2 output current capability
-

200
ppm/K
-120 -150

-200
mA mA mA mA
-
9397 750 14409
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Objective data sheet
Rev. 01 -- 10 August 2005
48 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol Vdet(UV)(V2) Parameter undervoltage detection threshold VBAT42 to VV3 voltage drop overload current detection threshold VBAT42 to VSYSINH voltage drop leakage current Conditions VBAT14 = 14 V Min 4.45 Typ 4.6 Max 4.75 Unit V
Voltage source; pin V3 VBAT42-V3(drop) Idet(OL)(V3) VBAT42 = 9 V to 52 V; IV3 = -20 mA VBAT42 = 9 V to 52 V -150 1.0 -60 V mA
System inhibit output; pin SYSINH VBAT42-SYSINH
(drop)
ISYSINH = -0.2 mA VSYSINH = 0 V
0.8 -
0.7 1.2 -
2.0 5 1.0 2.0 5
V A V V mA A
IL
Inhibit / limp home output; pin INH/LIMP VBAT14-INH(drop) VBAT14 to VINH voltage IINH/LIMP = -10 A; drop ILEN = ILC = 1 IINH/LIMP = -200 A; ILEN = ILC = 1 Io(INH/LIMP) IL output current capability leakage current VINH/LIMP = 0.4 V; ILEN = 1; ILC = 0 VINH/LIMP = 0 V to VBAT14; ILEN = 0
Wake input; pin WAKE Vth(WAKE) IWAKE(pu) VIH(th) VIL(th) Rpd(SCK) Rpd(SCS) ISDI WAKE voltage threshold pull-up input current HIGH-level input threshold voltage LOW-level input threshold voltage pull-down resistor at pin SCK pull-down resistor at pin SCS input leakage current at pin SDI HIGH-level output current LOW-level output current OFF-state output leakage current VSCK = 2 V; VV1 2 V VSCS = 1 V; VV1 2 V VSDI = 0 V to VV1 VWAKE = 0 V 2.0 -25 0.7 x VV1 -0.3 50 50 -5 3.3 130 130 5.0 -4 VV1 + 0.3 0.3 x VV1 400 400 +5 V A V V k k A
Serial peripheral interface inputs; pins SDI, SCK and SCS
Serial peripheral interface data output; pin SDO IOH IOL IOL(off)
9397 750 14409
VO = VV1 - 0.4 V VO = 0.4 V VO = 0 V to VV1
1.6 -5
-
-1.6 +5
mA mA A
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 -- 10 August 2005
49 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol IOH VOL VIH(th) VIL(th) Parameter HIGH-level output current LOW-level output voltage HIGH-level input threshold voltage LOW-level input threshold voltage HIGH-level output current LOW-level output current LOW-level output voltage LOW-level output current HIGH-level input voltage LOW-level input voltage TXDC pull-up resistor VTXDC = 0 V HIGH-level output current LOW-level output current CANH dominant output voltage CANL dominant output voltage Vo(m)(dom) VOH = VV1 - 0.4 V VOL = 0.4 V VOH = VV1 - 0.4 V VOL = 0.4 V IOL = 20 A; VV1 = 1.2 V Conditions VO = VV1 - 0.4 V; V1 = ON VV1 = 1.5 V to 5.5 V; pull-up resistor to V1 = 4 k Min 50 0 0.7 x VV1 -0.3 Typ Max 1000 Unit A Reset output with clamping detection; pin RSTN
0.15 x VV1 V VV1 + 0.3 V
+0.3 x VV1 V
Enable output; pin EN IOH IOL VOL 1.6 0 -1.6 0.4 mA mA V
Interrupt output; pin INTN IOL VOL = 0.4 V 1.6 mA
CAN transmit data input; pin TXDC VIH VIL RTXDC(pu) IOH IOL 0.7 x VV1 -0.3 5 1.6 12 VV1 + 0.3 V
+0.3 x VV1 V 25 -1.6 k mA mA
CAN receive data output; pin RXDC
High-speed CAN-bus lines; pins CANH and CANL Vo(dom) Active mode; VTXDC = 0 V; VV2 = 4.75 V to 5.25 V Active mode; VTXDC = 0 V; VV2 = 4.75 V to 5.25 V 3 0.5 -0.1 3.6 1.4 4.25 2 +0.15 V V V
matching of dominant RL = 60 ; Vo(m)(dom) = output voltage VV2 - VCANH - VCANL
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Objective data sheet
Rev. 01 -- 10 August 2005
50 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol Vo(dif) Parameter Conditions Min 1.5 Typ Max 3 Unit V differential bus output Active mode; VTXDC = 0 V; voltage VV2 = 4.75 V to 5.25 V; RL = 45 to 60 Active mode, On-line mode or On-line Listen mode; VTXDC = VV1; VV2 = 4.75 V to 5.25 V; no load VO(reces) recessive output voltage Active mode, On-line mode or On-line Listen mode; VTXDC = VV1; VV2 = 4.75 V to 5.25 V; RL = 60 Off-line mode; RL = 60 Vth((dif) differential receiver threshold voltage Active mode, On-line mode or On-line Listen mode; VCAN = -30 V to +30 V; RL = 60 Off-line mode; VCAN = -30 V to +30 V; RL = 60 ; measured from recessive to dominant Vth(GSD)(cm) common-mode bus voltage threshold level for ground shift detection Active mode; GSTHC = 0; VV2 = 5 V; RL = 60 ; (Vcm = (VCANH + VCANL) / 2) Active mode; GSTHC = 1; VV2 = 5 V; RL = 60 ; (Vcm = (VCANH + VCANL) / 2) Active mode; VCANH = -40 V; VTXDC = 0 V; VV2 = 5 V Active mode; VCANL = 40 V; VTXDC = 0 V; VV2 = 5 V all CAN modes; V2D = 1; VTXDC = VV1; VCAN = -40 V to +40 V Active mode, On-line mode or On-line Listen mode; V2D = 0; VTXDC = VV1; VCAN = -0.5 V to +8 V Ri input resistance Active mode, On-line mode or On-line Listen mode; V2D = 1; VTXDC = VV1; VCAN = -40 V to +40 V Off-line mode; VCAN = -40 V to +40 V
-50
0
+50
mV
2.25
2.5
2.75
V
-0.1 0.5
0 0.7
+0.1 0.9
V V
0.45
0.8
1.15
V
0.95
1.75
2.45
V
0.3
1
1.5
V
Io(CANH)(dom)
CANH dominant output current CANL dominant output current recessive output current
-100
-75
-45
mA
Io(CANL)(dom) Io(reces)
45 -5
75 -
100 +5
mA mA
-10
-
+10
A
9
15
28
k
15
22
40
k
9397 750 14409
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Objective data sheet
Rev. 01 -- 10 August 2005
51 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol Ri(m) Ri(dif) Ci(cm) Ci(dif) Rsc(bus) Parameter input resistance matching differential input resistance common-mode input capacitance differential input capacitance detectable short-circuit resistance between bus lines and VV2, VBAT14, VBAT42 and GND output voltage Active mode; VTXDC = 0 V
[2]
Conditions VCANH = VCANL
Min 19 -
Typ 0 30 -
Max 51 20 10 50
Unit % k pF pF
[2]
CAN-bus common mode stabilization output; pin SPLIT Vo Active mode, On-line mode or On-line Listen mode; CSO = V2D = 1; ISPLIT = 500 A Off-line mode OR CSO = 0; VSPLIT = -40 V to +40 V 0.3 x VV2 0.5 x VV2 0.7 x VV2 V
IL
leakage current
-10
-
+10
A
LIN transmit data input; pin TXDL VIL VIH RTXDL(pu) IOH IOL LOW level input voltage HIGH-level input voltage TXDL pull-up resistor HIGH-level output current LOW-level output current LIN dominant output voltage VTXDL = 0 V VRXDL = VV1 - 0.4 V VRXDL = 0.4 V -0.3 0.7 x VV1 5 1.6 12 0.3 x VV1 VV1 + 0.3 25 -1.6 V V k mA mA
LIN receive data output; pin RXDL
LIN-bus line; pin LIN Vo(dom) Normal mode; VBAT42 = 7 V to 18 V; LDC = 0; t < tTXDL(dom); VTXDL = 0 V; RBAT42-LIN = 500 Normal mode; VBAT42 = 7 V to 18 V; LDC = 1; t < tTXDL(dom); VTXDL = 0 V; ILIN = 40 mA ILIH HIGH-level input leakage current VLIN = VBAT42; VTXDL = VV1 0 0.20 x VBAT42 V
0
1.4
2.1
V
-10
0
+10
A
9397 750 14409
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Objective data sheet
Rev. 01 -- 10 August 2005
52 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol Io(sc) Parameter short-circuit output current Conditions Normal mode; VLIN = VBAT42 = 12 V; VTXDL = 0 V; t < tTXDL(dom); LDC = 0 Normal mode; VLIN = VBAT42 = 18 V; VTXDL = 0 V; t < tTXDL(dom); LDC = 0 Vth(dom) Vth(reces) Vth(cen) Ci IL receiver dominant state receiver recessive state receiver threshold voltage centre input capacitance leakage current VLIN = 0 V to 18 V VBAT42 = 0 V Active mode; IRTLIN = -10 A; VBAT42 = 7 V to 27 V Off-line mode; IRTLIN = -10 A; VBAT42 = 7 V to 27 V VRTLIN RTLIN load regulation Active mode; IRTLIN = -10 A to -10 mA; VBAT42 = 7 V to 27 V RTLIN pull-up current Active mode; VRTLIN = VLIN = 0 V (t > tLIN(dom)) Off-line mode; VRTLIN = VLIN = 0 V (t < tLIN(dom)) ILL LOW-level leakage current Off-line mode; VRTLIN = VLIN = 0 V [t > tLIN(dom)] for entering Software Development mode; Tj = 0 C to 50 C for entering Forced Normal mode; Tj = 0 C to 50 C R(pd)TEST pull-down resistor between pin TEST and GND Normal mode; VBAT42 = 7 V to 27 V Normal mode; VBAT42 = 7 V to 27 V Normal mode; VBAT42 = 7 V to 27 V
[2]
Min 27
Typ 40
Max 60
Unit mA
40

mA
0.6 x VBAT42 0.475 x VBAT42 -5
0.500 x VBAT42 -
0.4 x VBAT42 0.525 x VBAT42 10 +5
V V V pF A
LIN-bus termination resistor connection; pin RTLIN VRTLIN RTLIN output voltage VBAT42 - 1.0 VBAT42 - 1.2 VBAT42 - 0.7 VBAT42 - 1.0 0.65 VBAT42 - 0.2 V
V
2
V
IRTLIN(pu)
-150
-60
-35
A
-150
-60
-35
A
-10
0
+10
A
TEST input; pin TEST Vth(TEST) input threshold voltage 7 7.5 V
14 2
4
14.5 8
V k
9397 750 14409
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 -- 10 August 2005
53 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 26: Characteristics ...continued Tvj = -40 C to +150 C, VBAT42 = 5.5 V to 52 V and VBAT14 = 5.5 V to 27 V, unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol Tj(warn) Parameter high junction temperature warning level Conditions Min 160 Typ 175 Max 190 Unit C Temperature detection
[1] [2] [3]
VV1(nom) is 3 V, 3.3 V or 5 V, depending on the SBC version. Not tested in production. V2 internally supplies the SBC CAN transceiver. The performance of the CAN transceiver can be impaired if V2 is also used to supply other circuitry while the CAN transceiver is in use.
9. Dynamic characteristics
Table 27: Characteristics Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol Tcyc tlead tlag tSCKH tSCKL tsu th tDOV tSSH tSSL tt(reces-dom) Parameter clock cycle time enable lead time enable lag time clock HIGH time clock LOW time input data setup time input data hold time output data valid time pin SDO, CL = 10 pF SPI select HIGH time SPI select LOW time output transition time 10 % to 90 %; C = 100 pF; recessive to dominant R = 60 ; see Figure 17 and Figure 18 output transition time 90 % to 10 %; C = 100 pF; dominant to recessive R = 60 ; see Figure 17 and Figure 18 propagation delay TXDC to RXDC (HIGH-to-LOW transition) 50 % VTXDC to 50 % VRXDC; C = 100 pF; R = 60 ; see Figure 17 and Figure 18 clock is low when SPI select falls clock is low when SPI select rises Conditions Min 480 240 240 190 190 100 100 200 200 Typ 100 Max 100 Unit ns ns ns ns ns ns ns ns ns ns ns Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 21)
CAN transceiver timing; pins CANL, CANH, TXDC and RXDC
tt(dom-reces)
-
100
-
ns
tPHL
-
150
220
ns
9397 750 14409
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 -- 10 August 2005
54 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 27: Characteristics ...continued Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol tPLH Parameter propagation delay TXDC to RXDC (LOW-to-HIGH transition) Conditions 50 % VTXDC to 50 % VRXDC; C = 100 pF; R = 60 ; see Figure 17 and Figure 18 Min Typ 150 Max 220 Unit ns
tTXDC(dom)
TXDC permanent Active mode, On-line mode or dominant disable time On-line Listen mode; VV2 = 5 V; VTXDC = 0 V minimum dominant time first pulse for wake-up on pins CANH and CANL minimum recessive time pulse (after first dominant) for wake-up on pins CANH and CANL Off-line mode
1.5
-
6
ms
tCANH(dom1), tCANL(dom1)
3
-
-
s
tCANH(reces), tCANL(reces)
Off-line mode
1
-
-
s
tCANH(dom2), tCANL(dom2)
Off-line mode minimum dominant time second pulse for wake-up on pins CANH, CANL On-line Listen mode time-out period between wake-up message and confirm message minimum time before entering Off-line mode On-line or On-line Listen mode; TXDC = V1; V2D = 1; COTC = 0; no bus activity On-line or On-line Listen mode; TXDC = V1; V2D = 1; COTC = 1; no bus activity
1
-
-
s
ttimeout
115
-
285
ms
toff-line
50
-
66
ms
200
-
265
ms
toff-line(ext)
extended minimum time before entering Off-line mode
On-line or On-line Listen mode after CAN wake-up event; TXDC = V1; V2D = 1; no bus activity Vth(reces)(max) = 0.744 x VBAT42; Vth(dom)(max) = 0.581 x VBAT42; LSC = 0; tbit = 50 s; VBAT42 = 7 V to 27 V Vth(reces)(min) = 0.422 x VBAT42; Vth(dom)(min) = 0.284 x VBAT42; LSC = 0; tbit = 50 s; VBAT42 = 7.6 V to 27 V
[2]
400
-
530
ms
LIN transceiver; pins LIN, TXDL and RXDL [1] 1 duty cycle 1 0.396 -
2
duty cycle 2
[3]
-
-
0.581
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 27: Characteristics ...continued Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol 3 Parameter duty cycle 3 Conditions Vth(reces)(max) = 0.778 x VBAT42; Vth(dom)(max) = 0.616 x VBAT42; LSC = 1; tbit = 96 s; VBAT42 = 7 V to 27 V Vth(reces)(min) = 0.389 x VBAT42; Vth(dom)(min) = 0.251 x VBAT42; LSC = 1; tbit = 96 s; VBAT42 = 7.6 V to 27 V CRXDL = 20 pF rising edge with respect to falling edge; CRXDL = 20 pF Off-line mode
[2]
Min 0.417
Typ -
Max -
Unit
4
duty cycle 4
[3]
-
-
0.590
tp(rx) tp(rx)(sym) tBUS(LIN)
propagation delay of receiver symmetry of receiver propagation delay minimum dominant time for wake-up of the LIN-transceiver continuously dominant clamped LIN-bus detection time continuously dominant clamped LIN-bus recovery time
-2 30
-
6 +2 150
s s s
tLIN(dom)(det)
Active mode; LIN = 0 V
40
-
160
ms
tLIN(dom)(rec)
Active mode
0.8
-
2.2
ms
tTXDL(dom)(dis)
TXDL permanent Active mode; TXDL = 0 V dominant disable time BAT42 LOW time for setting PWONS BAT42 LOW time for setting BATFI V1 clamped LOW time during ramp-up of V1 V2 clamped LOW time during ramp-up of V2 cyclic sense period cyclic sense on-time Start-up mode; V1 active
20
-
80
ms
Battery monitoring tBAT42(L) tSENSE(L) 5 5 20 20 s s
Power supply V1; pin V1 tV1(CLT) 229 283 ms
Power supply V2; pin V2 t2(CLT) V2 active 28 36 ms
Power supply V3; pin V3 tW(CS) ton(CS) V3C = 10; see Figure 14 V3C = 11; see Figure 14 V3C = 10; see Figure 14 V3C = 11; see Figure 14
9397 750 14409
14 28 345 345
-
18 36 423 423
ms ms s s
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 27: Characteristics ...continued Tvj = -40 C to + 150 C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient temperature on wafer level (pre-testing). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. Symbol tWU(ipf) tsu(CS) Watchdog tWD(ETP) earliest watchdog trigger point latest watchdog trigger point programmed Nominal Watchdog Period (NWP); Normal mode programmed nominal watchdog period; Normal mode, Standby mode and Sleep mode watchdog time-out in Start-up mode Fail-safe mode; wake-up detected RSTN driven LOW internally but RSTN pin remains HIGH RSTN driven HIGH internally but RSTN pin remains LOW INTN = 0 after internal or external reset has been released; RST = 0 after internal or external reset has been released; RST =1 Interrupt output; pin INTN tINTN Oscillator fosc
[1]
Parameter input port filter time cyclic sense sample setup time
Conditions VBAT42 = 5 V to 27 V VBAT42 = 27 V to 52 V V3C = 11 or 10; see Figure 14
Min 10 50 310
Typ -
Max 120 250 390
Unit s s s
Wake-up input; pin WAKE
0.45 x NWP
-
0.55 x NWP 1.1 x NWP
tWD(LTP)
0.9 x NWP -
tWD(init) Fail-safe mode tret
watchdog initializing period retention time
229
-
283
ms
1.3
1.5
1.7
s
Reset output; pin RSTN tRSTN(CHT) tRSTN(CLT) tRSTN(INT) tRSTNL clamped HIGH time, pin RSTN clamped LOW time, pin RSTN interrupt monitoring time reset lengthening time 115 229 229 0.9 18 141 283 283 1.1 22 ms ms ms ms ms
interrupt release
after SPI has read out the Interrupt register
2
-
-
s
oscillator frequency
460.8
512
563.2
kHz
tbit = selected bit time, depends on LSC-bit; 50 s or 96 s (20 or 10.4 kbit/s respectively); bus load conditions (R1/R2/C1): 1 k/1 k/10 nF; 1 k/1 k/6.8 nF; 1 k/open/1 nF; see Figure 19 and Figure 20.
[2]
t BUS ( rec ) ( min ) D1, D3 = --------------------------------2 x t bit t BUS ( rec ) ( max ) D2, D4 = ---------------------------------2 x t bit
[3]
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
V1 dissipation
V2 dissipation
V3 dissipation
other dissipation
Tvj
8 K/W 25 K/W 29 K/W 6 K/W
4 K/W
Tcase(heat sink)
Rth(c-a)
Tamb
001aac327
Fig 16. Thermal model of the HTTSOP32 package
BAT42 32 TXDC
BAT14 27 20 V2 CANL R C Cb +5 V
13
22
UJA1065
RXDC 14 23
10 pF
21 GND
CANH
001aac308
Fig 17. Timing test circuit for CAN-transceiver
HIGH TXDC LOW CANH
CANL dominant(BUSon) 0.9 V 0.5 V VO(dif)(bus) RXDC 0.7 V1 0.3 V1 recessive(BUSoff) HIGH
LOW td(TXD-BUSoff) tPD(TXD-RXD)
001aac309
td(TXD-BUSon) tPD(TXD-RXD)
Fig 18. Timing diagram CAN transceiver
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
BAT42 RXDL
20 pF
RTLIN
UJA1065
TXDL GND LIN
R1
R2
C1
001aad179
Fig 19. Timing test circuit for LIN transceiver
tbit VTXDL
tbit
tbit
tbus(dom)(max) VBAT42(1)
tbus(rec)(min)
Vth(rec)(max) LIN BUS signal Vth(dom)(max) Vth(rec)(min) Vth(dom)(min)
thresholds of receiving node 1
thresholds of receiving node 2
tbus(dom)(min) receiving node 1 VRXDL1
tbus(rec)(max)
tp(rx1)f receiving node 2 VRXDL2
tp(rx1)r
tp(rx2)r
tp(rx2)f
001aaa346
(1) LIN Physical Layer Spec Rev. 2.0 (Sep 23, 2003) definition of bus timing parameters. Nodes 1 and 2 represent both
Fig 20. Timing diagram LIN transceiver
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
SCS tlead TSCK tSCKH tSCKL tlag tSSH
SCK
tsu
th
SDI
X
MSB tDOV
LSB
X
floating SDO X MSB LSB
floating
001aaa405
Fig 21. SPI timing
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High-speed CAN/LIN fail-safe system basis chip
10. Package outline
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
D
E
A X
c y exposed die pad side HE vMA
Z
Dh
32
17
Eh pin 1 index
A2 A1
(A3)
A
Lp L
1
e bp
16
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.1 10.9 Dh 5.1 4.9 E(2) 6.2 6.0 Eh 3.6 3.4 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 99-03-04 03-04-07
Fig 22. Package outline SOT 549-1 (HTSSOP32)
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
11. Soldering
11.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
11.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
11.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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High-speed CAN/LIN fail-safe system basis chip
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
11.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
11.5 Package related soldering information
Table 28: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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UJA1065
High-speed CAN/LIN fail-safe system basis chip
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
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High-speed CAN/LIN fail-safe system basis chip
12. Revision history
Table 29: Revision history Release date 20050810 Data sheet status Objective data sheet Change notice Doc. number 9397 750 14409 Supersedes Document ID UJA1065_1
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High-speed CAN/LIN fail-safe system basis chip
13. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
14. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
16. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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High-speed CAN/LIN fail-safe system basis chip
18. Contents
1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power management . . . . . . . . . . . . . . . . . . . . . 3 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Fail-safe system controller . . . . . . . . . . . . . . . . 7 Start-up mode. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . 9 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog start-up behavior . . . . . . . . . . . . . . 13 Watchdog window behavior . . . . . . . . . . . . . . 13 Watchdog time-out behavior . . . . . . . . . . . . . . 13 Watchdog OFF behavior. . . . . . . . . . . . . . . . . 14 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17 BAT14, BAT42 and SYSINH . . . . . . . . . . . . . . 17 SENSE input. . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage regulators V1 and V2 . . . . . . . . . . . . . 17 Switched battery output V3. . . . . . . . . . . . . . . 18 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . 18 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CAN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . 20 Termination control . . . . . . . . . . . . . . . . . . . . . 21 Bus, RXD and TXD failure detection. . . . . . . . 21 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 22 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . . 22 LIN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Termination control . . . . . . . . . . . . . . . . . . . . . 24 LIN driver capability . . . . . . . . . . . . . . . . . . . . 24 Bus and TXDL failure detection . . . . . . . . . . . 25 6.9 6.10 6.11 6.12 6.13 6.13.1 6.13.2 6.13.3 6.13.4 6.13.5 6.13.6 6.13.7 6.13.8 6.13.9 6.13.10 6.13.11 6.13.12 6.14 6.14.1 6.14.2 7 8 9 10 11 11.1 11.2 11.3 11.4 11.5 12 13 14 15 16 17 Inhibit and limp home output . . . . . . . . . . . . . Wake-up input . . . . . . . . . . . . . . . . . . . . . . . . Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . Temperature protection . . . . . . . . . . . . . . . . . SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . SPI register mapping . . . . . . . . . . . . . . . . . . . Register overview. . . . . . . . . . . . . . . . . . . . . . Mode register . . . . . . . . . . . . . . . . . . . . . . . . . System status register . . . . . . . . . . . . . . . . . . System diagnosis register . . . . . . . . . . . . . . . Interrupt enable register and interrupt enable feedback register . . . . . . . . . . . . . . . . . . . . . . Interrupt register. . . . . . . . . . . . . . . . . . . . . . . System configuration register and system configuration feedback register . . . . . . . . . . . Physical layer control register and physical layer control feedback register . . . . . . . . . . . . Special mode register and special mode feedback register . . . . . . . . . . . . . . . . . . . . . . General purpose registers and general purpose feedback registers . . . . . . . . . . . . . . Register configurations at reset . . . . . . . . . . . Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . Software Development mode . . . . . . . . . . . . . Forced Normal mode . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 25 26 27 27 28 29 29 29 32 34 35 36 38 39 40 40 41 44 44 44 45 46 55 62 63 63 63 63 64 64 66 67 67 67 67 67
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 10 August 2005 Document number: 9397 750 14409
Published in The Netherlands

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